#ifndef _ISP_REG_H_
#define _ISP_REG_H_

#include "vi_reg_fields.h"
#include "vi_reg_blocks.h"
#include "vi_vreg_blocks.h"

#define ISP_TOP_PHY_REG_BASE    (0x0A000000)

#define VREG_SIZE               (sizeof(struct VREG_RESV))
#define ADMA_DESC_SIZE          (sizeof(struct ISPCQ_ADMA_DESC_T))

/* ISP REG FIELD DEFINE */

/* ISP BLOCK ADDR OFFSET DEFINE */
#define ISP_BLK_BA_PRE_RAW_FE0     (0x00000000)
#define ISP_BLK_BA_CSIBDG0         (0x00000800)
#define ISP_BLK_BA_DMA_CTL6        (0x00000B00)
#define ISP_BLK_BA_DMA_CTL7        (0x00000C00)
#define ISP_BLK_BA_DMA_CTL8        (0x00000D00)
#define ISP_BLK_BA_DMA_CTL9        (0x00000E00)
#define ISP_BLK_BA_BLC0            (0x00001000)
#define ISP_BLK_BA_BLC1            (0x00001800)
#define ISP_BLK_BA_RGBMAP0         (0x00002000)
#define ISP_BLK_BA_WBG2            (0x00002100)
#define ISP_BLK_BA_DMA_CTL10       (0x00002200)
#define ISP_BLK_BA_RGBMAP1         (0x00002300)
#define ISP_BLK_BA_WBG3            (0x00002400)
#define ISP_BLK_BA_DMA_CTL11       (0x00002500)

#define ISP_BLK_BA_PRE_RAW_FE1     (0x00008000)
#define ISP_BLK_BA_CSIBDG1         (0x00008800)
#define ISP_BLK_BA_DMA_CTL12       (0x00008B00)
#define ISP_BLK_BA_DMA_CTL13       (0x00008C00)
#define ISP_BLK_BA_DMA_CTL14       (0x00008D00)
#define ISP_BLK_BA_DMA_CTL15       (0x00008E00)
#define ISP_BLK_BA_BLC2            (0x00009000)
#define ISP_BLK_BA_BLC3            (0x00009800)
#define ISP_BLK_BA_RGBMAP2         (0x0000A000)
#define ISP_BLK_BA_WBG4            (0x0000A100)
#define ISP_BLK_BA_DMA_CTL16       (0x0000A200)
#define ISP_BLK_BA_RGBMAP3         (0x0000A300)
#define ISP_BLK_BA_WBG5            (0x0000A400)
#define ISP_BLK_BA_DMA_CTL17       (0x0000A500)

#define ISP_BLK_BA_PRE_RAW_FE2     (0x00010000)
#define ISP_BLK_BA_CSIBDG2         (0x00010800)
#define ISP_BLK_BA_DMA_CTL18       (0x00010B00)
#define ISP_BLK_BA_DMA_CTL19       (0x00010C00)
#define ISP_BLK_BA_BLC4            (0x00011000)
#define ISP_BLK_BA_RGBMAP4         (0x00012000)
#define ISP_BLK_BA_WBG6            (0x00012100)
#define ISP_BLK_BA_DMA_CTL20       (0x00012200)

#define ISP_BLK_BA_PRE_RAW_BE      (0x00018000)
#define ISP_BLK_BA_CROP0           (0x00018800)
#define ISP_BLK_BA_CROP1           (0x00019000)
#define ISP_BLK_BA_BLC5            (0x00019800)
#define ISP_BLK_BA_BLC6            (0x0001A000)
#define ISP_BLK_BA_AF              (0x0001A800)
#define ISP_BLK_BA_DMA_CTL21       (0x0001AA00)
#define ISP_BLK_BA_DPC0            (0x0001B000)
#define ISP_BLK_BA_DPC1            (0x0001B100)
#define ISP_BLK_BA_DMA_CTL22       (0x0001B800)
#define ISP_BLK_BA_DMA_CTL23       (0x0001B880)
#define ISP_BLK_BA_PRE_WDMA        (0x0001B900)
#define ISP_BLK_BA_PCHK0           (0x0001C000)
#define ISP_BLK_BA_PCHK1           (0x0001C800)

#define ISP_BLK_BA_RAWTOP          (0x00030000)
#define ISP_BLK_BA_CFA             (0x00031000)
#define ISP_BLK_BA_LSC             (0x00032000)
#define ISP_BLK_BA_DMA_CTL24       (0x00032100)
#define ISP_BLK_BA_GMS             (0x00033000)
#define ISP_BLK_BA_DMA_CTL25       (0x00033100)
#define ISP_BLK_BA_AEHIST0         (0x00034000)
#define ISP_BLK_BA_DMA_CTL26       (0x00034400)
#define ISP_BLK_BA_AEHIST1         (0x00035000)
#define ISP_BLK_BA_DMA_CTL27       (0x00035400)
#define ISP_BLK_BA_DMA_CTL28       (0x00036000)
#define ISP_BLK_BA_DMA_CTL29       (0x00036080)
#define ISP_BLK_BA_RAW_RDMA        (0x00036100)
#define ISP_BLK_BA_BNR             (0x0003C000)
#define ISP_BLK_BA_CROP2           (0x0003D000)
#define ISP_BLK_BA_CROP3           (0x0003E000)
#define ISP_BLK_BA_LMAP0           (0x0003F000)
#define ISP_BLK_BA_DMA_CTL30       (0x0003F100)
#define ISP_BLK_BA_LMAP1           (0x0003F200)
#define ISP_BLK_BA_DMA_CTL31       (0x0003F300)
#define ISP_BLK_BA_WBG0            (0x00040000)
#define ISP_BLK_BA_WBG1            (0x00041000)
#define ISP_BLK_BA_PCHK2           (0x00042000)
#define ISP_BLK_BA_PCHK3           (0x00043000)
#define ISP_BLK_BA_LCAC            (0x00044000)
#define ISP_BLK_BA_RGBCAC          (0x00045000)

#define ISP_BLK_BA_RGBTOP          (0x00050000)
#define ISP_BLK_BA_CCM0            (0x00052000)
#define ISP_BLK_BA_CCM1            (0x00052100)
#define ISP_BLK_BA_RGBGAMMA        (0x00052200)
#define ISP_BLK_BA_YGAMMA          (0x00052300)
#define ISP_BLK_BA_MMAP            (0x00053000)
#define ISP_BLK_BA_DMA_CTL32       (0x00053200)
#define ISP_BLK_BA_DMA_CTL33       (0x00053300)
#define ISP_BLK_BA_DMA_CTL34       (0x00053400)
#define ISP_BLK_BA_DMA_CTL35       (0x00053500)
#define ISP_BLK_BA_DMA_CTL36       (0x00053600)
#define ISP_BLK_BA_DMA_CTL37       (0x00053700)
#define ISP_BLK_BA_CLUT            (0x00054000)
#define ISP_BLK_BA_DHZ             (0x00055000)
#define ISP_BLK_BA_CSC             (0x00056000)
#define ISP_BLK_BA_RGBDITHER       (0x00057000)
#define ISP_BLK_BA_PCHK4           (0x00059000)
#define ISP_BLK_BA_PCHK5           (0x0005A000)
#define ISP_BLK_BA_HIST_V          (0x0005C000)
#define ISP_BLK_BA_DMA_CTL38       (0x0005C100)
#define ISP_BLK_BA_HDRFUSION       (0x0005D000)
#define ISP_BLK_BA_HDRLTM          (0x0005E000)
#define ISP_BLK_BA_DMA_CTL39       (0x0005E100)
#define ISP_BLK_BA_DMA_CTL40       (0x0005E200)

#define ISP_BLK_BA_YUVTOP          (0x00060000)
#define ISP_BLK_BA_TNR             (0x00061000)
#define ISP_BLK_BA_DMA_CTL41       (0x00061800)
#define ISP_BLK_BA_DMA_CTL42       (0x00061900)
#define ISP_BLK_BA_FBCE            (0x00061A00)
#define ISP_BLK_BA_DMA_CTL43       (0x00061B00)
#define ISP_BLK_BA_DMA_CTL44       (0x00061C00)
#define ISP_BLK_BA_FBCD            (0x00061D00)
#define ISP_BLK_BA_YUVDITHER       (0x00061E00)
#define ISP_BLK_BA_CA              (0x00062000)
#define ISP_BLK_BA_CA_LITE         (0x00063000)
#define ISP_BLK_BA_YNR             (0x00064000)
#define ISP_BLK_BA_CNR             (0x00065000)
#define ISP_BLK_BA_EE              (0x00066000)
#define ISP_BLK_BA_YCURVE          (0x00067000)
#define ISP_BLK_BA_DCI             (0x00068000)
#define ISP_BLK_BA_DMA_CTL45       (0x00068100)
#define ISP_BLK_BA_DCI_GAMMA       (0x00068200)
#define ISP_BLK_BA_CROP4           (0x00069000)
#define ISP_BLK_BA_DMA_CTL46       (0x00069100)
#define ISP_BLK_BA_CROP5           (0x0006A000)
#define ISP_BLK_BA_DMA_CTL47       (0x0006A100)
#define ISP_BLK_BA_LDCI            (0x0006B000)
#define ISP_BLK_BA_DMA_CTL48       (0x0006B300)
#define ISP_BLK_BA_DMA_CTL49       (0x0006B400)
#define ISP_BLK_BA_PRE_EE          (0x0006C000)
#define ISP_BLK_BA_PCHK6           (0x0006D000)
#define ISP_BLK_BA_PCHK7           (0x0006E000)

#define ISP_BLK_BA_ISPTOP          (0x00070000)
#define ISP_BLK_BA_WDMA_CORE0      (0x00072000)
#define ISP_BLK_BA_RDMA_CORE       (0x00074000)
#define ISP_BLK_BA_CSIBDG_LITE     (0x00076000)
#define ISP_BLK_BA_DMA_CTL0        (0x00076200)
#define ISP_BLK_BA_DMA_CTL1        (0x00076300)
#define ISP_BLK_BA_DMA_CTL2        (0x00076400)
#define ISP_BLK_BA_DMA_CTL3        (0x00076500)
#define ISP_BLK_BA_WDMA_CORE1      (0x00078000)
#define ISP_BLK_BA_PRE_RAW_VI_SEL  (0x0007F400)
#define ISP_BLK_BA_DMA_CTL4        (0x0007F500)
#define ISP_BLK_BA_DMA_CTL5        (0x0007F600)
#define ISP_BLK_BA_CMDQ            (0x0007FC00)

enum ISP_BLK_ID_T {
	ISP_BLK_ID_PRE_RAW_FE0,
	ISP_BLK_ID_CSIBDG0,
	ISP_BLK_ID_DMA_CTL6,
	ISP_BLK_ID_DMA_CTL7,
	ISP_BLK_ID_DMA_CTL8,
	ISP_BLK_ID_DMA_CTL9,
	ISP_BLK_ID_BLC0,
	ISP_BLK_ID_BLC1,
	ISP_BLK_ID_RGBMAP0,
	ISP_BLK_ID_WBG2,
	ISP_BLK_ID_DMA_CTL10, //10
	ISP_BLK_ID_RGBMAP1,
	ISP_BLK_ID_WBG3,
	ISP_BLK_ID_DMA_CTL11, //13
	ISP_BLK_ID_PRE_RAW_FE1,
	ISP_BLK_ID_CSIBDG1,
	ISP_BLK_ID_DMA_CTL12,
	ISP_BLK_ID_DMA_CTL13,
	ISP_BLK_ID_DMA_CTL14,
	ISP_BLK_ID_DMA_CTL15,
	ISP_BLK_ID_BLC2,
	ISP_BLK_ID_BLC3,
	ISP_BLK_ID_RGBMAP2,
	ISP_BLK_ID_WBG4,
	ISP_BLK_ID_DMA_CTL16,
	ISP_BLK_ID_RGBMAP3,
	ISP_BLK_ID_WBG5,
	ISP_BLK_ID_DMA_CTL17,
	ISP_BLK_ID_PRE_RAW_FE2,
	ISP_BLK_ID_CSIBDG2,
	ISP_BLK_ID_DMA_CTL18,
	ISP_BLK_ID_DMA_CTL19,
	ISP_BLK_ID_BLC4,
	ISP_BLK_ID_RGBMAP4,
	ISP_BLK_ID_WBG6,
	ISP_BLK_ID_DMA_CTL20,
	ISP_BLK_ID_PRE_RAW_BE,
	ISP_BLK_ID_CROP0,
	ISP_BLK_ID_CROP1,
	ISP_BLK_ID_BLC5,
	ISP_BLK_ID_BLC6,
	ISP_BLK_ID_AF,
	ISP_BLK_ID_DMA_CTL21,
	ISP_BLK_ID_DPC0,
	ISP_BLK_ID_DPC1,
	ISP_BLK_ID_DMA_CTL22, //45
	ISP_BLK_ID_DMA_CTL23, //46
	ISP_BLK_ID_PRE_WDMA,
	ISP_BLK_ID_PCHK0,
	ISP_BLK_ID_PCHK1,
	ISP_BLK_ID_RAWTOP,
	ISP_BLK_ID_CFA,
	ISP_BLK_ID_LSC,
	ISP_BLK_ID_DMA_CTL24, //53
	ISP_BLK_ID_GMS,
	ISP_BLK_ID_DMA_CTL25, //55
	ISP_BLK_ID_AEHIST0,
	ISP_BLK_ID_DMA_CTL26, //57
	ISP_BLK_ID_AEHIST1,
	ISP_BLK_ID_DMA_CTL27, //59
	ISP_BLK_ID_DMA_CTL28,
	ISP_BLK_ID_DMA_CTL29,
	ISP_BLK_ID_RAW_RDMA,
	ISP_BLK_ID_BNR,
	ISP_BLK_ID_CROP2,
	ISP_BLK_ID_CROP3,
	ISP_BLK_ID_LMAP0,
	ISP_BLK_ID_DMA_CTL30, //67
	ISP_BLK_ID_LMAP1,
	ISP_BLK_ID_DMA_CTL31,
	ISP_BLK_ID_WBG0,
	ISP_BLK_ID_WBG1,
	ISP_BLK_ID_PCHK2,
	ISP_BLK_ID_PCHK3,
	ISP_BLK_ID_LCAC,
	ISP_BLK_ID_RGBCAC,
	ISP_BLK_ID_RGBTOP,
	ISP_BLK_ID_CCM0,
	ISP_BLK_ID_CCM1,
	ISP_BLK_ID_RGBGAMMA,
	ISP_BLK_ID_YGAMMA,
	ISP_BLK_ID_MMAP,
	ISP_BLK_ID_DMA_CTL32,
	ISP_BLK_ID_DMA_CTL33,
	ISP_BLK_ID_DMA_CTL34,
	ISP_BLK_ID_DMA_CTL35,
	ISP_BLK_ID_DMA_CTL36, //86
	ISP_BLK_ID_DMA_CTL37,
	ISP_BLK_ID_CLUT,
	ISP_BLK_ID_DHZ,
	ISP_BLK_ID_CSC,
	ISP_BLK_ID_RGBDITHER,
	ISP_BLK_ID_PCHK4,
	ISP_BLK_ID_PCHK5,
	ISP_BLK_ID_HIST_V,
	ISP_BLK_ID_DMA_CTL38, //95
	ISP_BLK_ID_HDRFUSION,
	ISP_BLK_ID_HDRLTM,
	ISP_BLK_ID_DMA_CTL39,
	ISP_BLK_ID_DMA_CTL40,
	ISP_BLK_ID_YUVTOP,
	ISP_BLK_ID_TNR,
	ISP_BLK_ID_DMA_CTL41, //102
	ISP_BLK_ID_DMA_CTL42,
	ISP_BLK_ID_FBCE,
	ISP_BLK_ID_DMA_CTL43, //105
	ISP_BLK_ID_DMA_CTL44,
	ISP_BLK_ID_FBCD,
	ISP_BLK_ID_YUVDITHER,
	ISP_BLK_ID_CA,
	ISP_BLK_ID_CA_LITE,
	ISP_BLK_ID_YNR,
	ISP_BLK_ID_CNR,
	ISP_BLK_ID_EE,
	ISP_BLK_ID_YCURVE,
	ISP_BLK_ID_DCI,
	ISP_BLK_ID_DMA_CTL45, //116
	ISP_BLK_ID_DCI_GAMMA,
	ISP_BLK_ID_CROP4,
	ISP_BLK_ID_DMA_CTL46,
	ISP_BLK_ID_CROP5,
	ISP_BLK_ID_DMA_CTL47,
	ISP_BLK_ID_LDCI,
	ISP_BLK_ID_DMA_CTL48,
	ISP_BLK_ID_DMA_CTL49,
	ISP_BLK_ID_PRE_EE,
	ISP_BLK_ID_PCHK6,
	ISP_BLK_ID_PCHK7,
	ISP_BLK_ID_ISPTOP,
	ISP_BLK_ID_WDMA_CORE0,
	ISP_BLK_ID_RDMA_CORE,
	ISP_BLK_ID_CSIBDG_LITE,
	ISP_BLK_ID_DMA_CTL0,
	ISP_BLK_ID_DMA_CTL1,
	ISP_BLK_ID_DMA_CTL2,
	ISP_BLK_ID_DMA_CTL3,
	ISP_BLK_ID_WDMA_CORE1,
	ISP_BLK_ID_PRE_RAW_VI_SEL,
	ISP_BLK_ID_DMA_CTL4,
	ISP_BLK_ID_DMA_CTL5,
	ISP_BLK_ID_CMDQ,
	ISP_BLK_ID_MAX
};

#endif //_ISP_REG_H_
